(4190.201 002, prof. Taekyoung, Kwon)
Contact TA. Shim, if you want to claim.
¡Ü The final exam will be on Mon (6/16).
¡Ü You can submit the HW2 ASAP to Prof. Kwon or to TA. Shim. (during Prof. Kwon¡¯s absence)
But there is some penalty.
¡Ü There is a score of mid-term exam. ( Score )
Contact Prof. Kwon, if
you want to claim. (Claim period:
¡Ü If you want to take both "logic design" and "logic design lab" courses, please register for the courses of the same professor.
¡Ü There is no class on 3/3 and 3/5.
¡Ü Introduces elements consisting digital logic circuits and approaches to design digital logic circuits. Learn about combinational logic and sequential logic, basic elements of circuits and how to design optimized logic circuit. ( overview )
¡Ü Contemporary logic design, 2nd edition: Randy Katz, Gaetano Borriello, Prentice Hall
¡Ü Building 302, Room 107
MON/WED , AM10:30 ~
1. Introduction ( 01-intro )
2. Combinational Logic Design ( 02-Comb )
3. Working with Combinational Logic ( 03-WorkComb )
4. Combinational Logic Technologies ( 04-CombTech )
5. Case studies for Combinational Logic ( 05-CombEx )
6. Sequential Logic design ( 06-Seq )
n Mid-term Exam
8. Working with
9. Sequential Logic Technologies ( 09-SeqTech )
10. Case studies in Sequential Logic Design ( 10-SeqEx )
n Final exam
Verilog ( verilog-total )
2. HW2 ( hw2 )
Mid-term Exam : 30%
Final Exam : 30%
10. TA (Web)